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Explicitely specify cmp instructions to be 32 bits or 64bits on powerpc

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Signed-off-by: Thierry Fauck <tfauck@free.fr>

	modified:   stub/src/arch/powerpc/32/bxx.S
	modified:   stub/src/arch/powerpc/64le/bxx.S
	modified:   stub/src/arch/powerpc/64le/lzma_d.S
	modified:   stub/src/arch/powerpc/64le/nrv2b_d.S
	modified:   stub/src/arch/powerpc/64le/nrv2d_d.S
	modified:   stub/src/arch/powerpc/64le/nrv2e_d.S
	modified:   stub/src/powerpc64le-darwin.dylib-entry.S
	modified:   stub/src/powerpc64le-darwin.macho-entry.S
	modified:   stub/src/powerpc64le-darwin.macho-fold.S
	modified:   stub/src/powerpc64le-linux.elf-entry.S
	modified:   stub/src/powerpc64le-linux.elf-fold.S
	modified:   stub/src/powerpc64le-linux.kernel.vmlinux.S
This commit is contained in:
Thierry Fauck
2017-01-29 23:16:31 +01:00
committed by Markus F.X.J. Oberhumer
parent e1a8c932ee
commit 685953f6a5
12 changed files with 18 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/stub/src/arch/powerpc/32/bxx.S
+3 -3
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@@ -36,10 +36,10 @@ ppcbxx: # (*f_unf)(xo->buf, out_len, h.b_cto8, h.b_ftid);
#define ptr0 a4 #define ptr0 a4
cmpli cr0,ftid,0xd0; bnelr- cr0 # if (0xd0!=ftid) return; cmpli cr0,0,ftid,0xd0; bnelr- cr0 # if (0xd0!=ftid) return;
rlwinm. len,len,32-2,2,31; beqlr- cr0 # if (0==(len>>=2)) return; rlwinm. len,len,32-2,2,31; beqlr- cr0 # if (0==(len>>=2)) return;
lis r0,-(~0<<(32-16- (2+6+ W_CTO))) # limit in 32-bit words lis r0,-(~0<<(32-16- (2+6+ W_CTO))) # limit in 32-bit words
cmpl cr0,len,r0 cmpl cr0,0,len,r0
blt cr0,L5 blt cr0,L5
mr len,r0 mr len,r0
L5: L5:
@@ -58,7 +58,7 @@ L10:
L20: L20:
lwzu t0,4(ptr) # t0= *++ptr; lwzu t0,4(ptr) # t0= *++ptr;
rlwinm t1,t0,6+W_CTO,32-(6+W_CTO),31 # t1= top (6+W_CTO) bits of t0 rlwinm t1,t0,6+W_CTO,32-(6+W_CTO),31 # t1= top (6+W_CTO) bits of t0
cmpl cr0,t1,cto8; beq- cr0,L10 # unconditional branch marked with cto8; unlikely cmpl cr0,0,t1,cto8; beq- cr0,L10 # unconditional branch marked with cto8; unlikely
bdnz+ L20 # if (0!=--ctr) goto L20; // likely bdnz+ L20 # if (0!=--ctr) goto L20; // likely
ret ret
src/stub/src/arch/powerpc/64le/bxx.S
+3 -3
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@@ -36,10 +36,10 @@ ppcbxx: # (*f_unf)(xo->buf, out_len, h.b_cto8, h.b_ftid);
#define ptr0 a4 #define ptr0 a4
cmpli cr0,ftid,0xd0; bnelr- cr0 # if (0xd0!=ftid) return; cmpli cr0,0,ftid,0xd0; bnelr- cr0 # if (0xd0!=ftid) return;
rlwinm. len,len,32-2,2,31; beqlr- cr0 # if (0==(len>>=2)) return; rlwinm. len,len,32-2,2,31; beqlr- cr0 # if (0==(len>>=2)) return;
lis r0,-(~0<<(32-16- (2+6+ W_CTO))) # limit in 32-bit words lis r0,-(~0<<(32-16- (2+6+ W_CTO))) # limit in 32-bit words
cmpl cr0,len,r0 cmpl cr0,0,len,r0
blt cr0,L5 blt cr0,L5
mr len,r0 mr len,r0
L5: L5:
@@ -58,7 +58,7 @@ L10:
L20: L20:
lwzu t0,4(ptr) # t0= *++ptr; lwzu t0,4(ptr) # t0= *++ptr;
rlwinm t1,t0,6+W_CTO,32-(6+W_CTO),31 # t1= top (6+W_CTO) bits of t0 rlwinm t1,t0,6+W_CTO,32-(6+W_CTO),31 # t1= top (6+W_CTO) bits of t0
cmpl cr0,t1,cto8; beq- cr0,L10 # unconditional branch marked with cto8; unlikely cmpl cr0,0,t1,cto8; beq- cr0,L10 # unconditional branch marked with cto8; unlikely
bdnz+ L20 # if (0!=--ctr) goto L20; // likely bdnz+ L20 # if (0!=--ctr) goto L20; // likely
ret ret
src/stub/src/arch/powerpc/64le/lzma_d.S
+2 -2
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@@ -44,7 +44,7 @@ retaddr = 6*8 // (sp,cr,pc, xx,yy,zz) save area per calling convention
//// teq r0,r0 // debugging //// teq r0,r0 // debugging
#define M_LZMA 14 #define M_LZMA 14
cmpli cr0,meth,M_LZMA cmpli cr0,0,meth,M_LZMA
bne cr0,not_lzma bne cr0,not_lzma
mflr r0 mflr r0
@@ -82,7 +82,7 @@ retaddr = 6*8 // (sp,cr,pc, xx,yy,zz) save area per calling convention
stw r0,0(a6) // outSizeProcessed= 0; stw r0,0(a6) // outSizeProcessed= 0;
1: 1:
stwu r0,-4(a0) // clear CLZmaDecoderState on stack stwu r0,-4(a0) // clear CLZmaDecoderState on stack
cmpl cr0,sp,a0 // compare logical ==> compare unsigned cmpl cr0,0,sp,a0 // compare logical ==> compare unsigned
blt cr0,1b blt cr0,1b
stw a3,0(sp) // frame chain stw a3,0(sp) // frame chain
src/stub/src/arch/powerpc/64le/nrv2b_d.S
+1 -1
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@@ -33,7 +33,7 @@
dcbtst 0,dst // prime dcache for store dcbtst 0,dst // prime dcache for store
mflr t3 // return address mflr t3 // return address
cmpli cr0,meth,M_NRV2B_LE32 cmpli cr0,0,meth,M_NRV2B_LE32
bne cr0,not_nrv2b bne cr0,not_nrv2b
std dst,0(ldst) // original dst std dst,0(ldst) // original dst
src/stub/src/arch/powerpc/64le/nrv2d_d.S
+1 -1
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@@ -33,7 +33,7 @@
dcbtst 0,dst // prime dcache for store dcbtst 0,dst // prime dcache for store
mflr t3 // return address mflr t3 // return address
cmpli cr0,meth,M_NRV2D_LE32 cmpli cr0,0,meth,M_NRV2D_LE32
bne cr0,not_nrv2d bne cr0,not_nrv2d
std dst,0(ldst) // original dst std dst,0(ldst) // original dst
src/stub/src/arch/powerpc/64le/nrv2e_d.S
+1 -1
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@@ -33,7 +33,7 @@
dcbtst 0,dst // prime dcache for store dcbtst 0,dst // prime dcache for store
mflr t3 // return address mflr t3 // return address
cmpli cr0,meth,M_NRV2E_LE32 cmpli cr0,0,meth,M_NRV2E_LE32
bne cr0,not_nrv2e bne cr0,not_nrv2e
std dst,0(ldst) // original dst std dst,0(ldst) // original dst
src/stub/src/powerpc64le-darwin.dylib-entry.S
+2 -2
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@@ -101,7 +101,7 @@ CACHELINE=32
ori dst0,dst0,-1+ CACHELINE // highest addr on cache line ori dst0,dst0,-1+ CACHELINE // highest addr on cache line
cfl_nrv: cfl_nrv:
dcbst 0,dst0 // initiate store (modified) cacheline to memory dcbst 0,dst0 // initiate store (modified) cacheline to memory
cmpl cr0,dst0,dst // did we cover the highest-addressed byte? cmpl cr0,0,dst0,dst // did we cover the highest-addressed byte?
icbi 0,dst0 // discard instructions from cacheline icbi 0,dst0 // discard instructions from cacheline
addi dst0,dst0,CACHELINE // highest addr on next line addi dst0,dst0,CACHELINE // highest addr on next line
blt cr0,cfl_nrv // not done yet blt cr0,cfl_nrv // not done yet
@@ -265,7 +265,7 @@ dy_uncpr:
// FIXME: check status // FIXME: check status
lbz a3,b_ftid(s_cpr) lbz a3,b_ftid(s_cpr)
cmpli cr0,a3,0 cmpli cr0,0,a3,0
beq dy_uncpr beq dy_uncpr
lbz a2,b_cto8(s_cpr) lbz a2,b_cto8(s_cpr)
ld a1,sz_unc(s_cpr) ld a1,sz_unc(s_cpr)
src/stub/src/powerpc64le-darwin.macho-entry.S
+1 -1
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@@ -87,7 +87,7 @@ CACHELINE=32
ori dst0,dst0,-1+ CACHELINE // highest addr on cache line ori dst0,dst0,-1+ CACHELINE // highest addr on cache line
cfl_nrv: cfl_nrv:
dcbst 0,dst0 // initiate store (modified) cacheline to memory dcbst 0,dst0 // initiate store (modified) cacheline to memory
cmpl cr0,dst0,dst // did we cover the highest-addressed byte? cmpl cr0,0,dst0,dst // did we cover the highest-addressed byte?
icbi 0,dst0 // discard instructions from cacheline icbi 0,dst0 // discard instructions from cacheline
addi dst0,dst0,CACHELINE // highest addr on next line addi dst0,dst0,CACHELINE // highest addr on next line
blt cr0,cfl_nrv // not done yet blt cr0,cfl_nrv // not done yet
src/stub/src/powerpc64le-darwin.macho-fold.S
+1 -1
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@@ -71,7 +71,7 @@ L90:
lwz a1,-8(r31) # offset to {l_info; p_info; b_info} lwz a1,-8(r31) # offset to {l_info; p_info; b_info}
subf a0,a1,r31 # &l_info subf a0,a1,r31 # &l_info
lwz a3,sz_unc+sz_p_info+sz_l_info(a0) # sz_mach_headers lwz a3,sz_unc+sz_p_info+sz_l_info(a0) # sz_mach_headers
cmpli 0,a3,2048; bgt L100; li a3,2048 # at least 2 KiB for /usr/lib/dyld cmpli 0,0,a3,2048; bgt L100; li a3,2048 # at least 2 KiB for /usr/lib/dyld
L100: L100:
movr r29,sp # remember for restoring later movr r29,sp # remember for restoring later
subf sp,a3,sp # alloca subf sp,a3,sp # alloca
src/stub/src/powerpc64le-linux.elf-entry.S
+1 -1
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@@ -114,7 +114,7 @@ CACHELINE=32
ori dst0,dst0,-1+ CACHELINE // highest addr on cache line ori dst0,dst0,-1+ CACHELINE // highest addr on cache line
cfl_nrv: cfl_nrv:
dcbst 0,dst0 // initiate store (modified) cacheline to memory dcbst 0,dst0 // initiate store (modified) cacheline to memory
cmpl cr0,dst0,dst // did we cover the highest-addressed byte? cmpl cr0,0,dst0,dst // did we cover the highest-addressed byte?
icbi 0,dst0 // discard instructions from cacheline icbi 0,dst0 // discard instructions from cacheline
addi dst0,dst0,CACHELINE // highest addr on next line addi dst0,dst0,CACHELINE // highest addr on next line
blt cr0,cfl_nrv // not done yet blt cr0,cfl_nrv // not done yet
src/stub/src/powerpc64le-linux.elf-fold.S
+1 -1
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@@ -65,7 +65,7 @@ fold_begin:
zfind: zfind:
ld t0,0(a6) // parameters are 16byte aligned ld t0,0(a6) // parameters are 16byte aligned
addi a6,a6,8 addi a6,a6,8
cmpi cr7,t0,0; bne+ cr7,zfind cmpi cr7,0,t0,0; bne+ cr7,zfind
ret ret
L90: L90:
la sp,LINKAREA(sp) // trim save area used by decompressor la sp,LINKAREA(sp) // trim save area used by decompressor
src/stub/src/powerpc64le-linux.kernel.vmlinux.S
+1 -1
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@@ -116,7 +116,7 @@ CACHELINE=32
ori dst0,dst0,-1+ CACHELINE // highest addr on cache line ori dst0,dst0,-1+ CACHELINE // highest addr on cache line
cfl_nrv: cfl_nrv:
dcbst 0,dst0 // initiate store (modified) cacheline to memory dcbst 0,dst0 // initiate store (modified) cacheline to memory
cmpl cr0,dst0,dst // did we cover the highest-addressed byte? cmpl cr0,0,dst0,dst // did we cover the highest-addressed byte?
icbi 0,dst0 // discard instructions from cacheline icbi 0,dst0 // discard instructions from cacheline
addi dst0,dst0,CACHELINE // highest addr on next line addi dst0,dst0,CACHELINE // highest addr on next line
blt cr0,cfl_nrv // not done yet blt cr0,cfl_nrv // not done yet