cacheflush
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@ -65,6 +65,17 @@ M_NRV2B_LE32=2 // ../conf.h
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M_NRV2D_LE32=5
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M_NRV2E_LE32=8
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/* These from /usr/include/asm/unistd.h */
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__NR_Linux = 4000
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__NR_write = 4+ __NR_Linux
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__NR_exit = 1+ __NR_Linux
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__NR_mmap = 90+ __NR_Linux
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__NR_cacheflush = 147+ __NR_Linux
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/* asm/cachectl.h */
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ICACHE= 1<<0
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DCACHE= 1<<1
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//BAL=0x04110000
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section ELFMAINX
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@ -120,7 +131,7 @@ LZMA_LIT_NUM = 768
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lxlzma_szframe = 12*4
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lxlzma_sv_pc = 11*4
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lxlzma_sv_sp = 10*4
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/* 9 */
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lxlzma_dst = 9*4
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lxlzma_dstdone = 8*4
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lxlzma_srcdone = 7*4
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@ -140,6 +151,7 @@ lxlzma_srcdone = 7*4
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addiu a6,sp,lxlzma_dstdone
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sw ra, lxlzma_sv_pc(sp)
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lw a5,0(lxdstlen)
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sw lxdst,lxlzma_dst(sp)
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move a4,lxdst
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addiu a3,sp,lxlzma_srcdone
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addiu a2,lxsrclen,-2 # 2 header bytes
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@ -151,13 +163,37 @@ lxlzma_srcdone = 7*4
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srl t8,t8,4
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bal lzma_decode
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sb t8,1(a0) # lit_pos_bits
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/* It seems that for our uses the icache does not need to be invalidated,
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because no lines from the destination have ever been fetched. However,
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if the dcache is write-back, then some of the results might not be in
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memory yet, and the icache could fetch stale data; so memory must be
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updated from dcache.
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The *next* call of the decompressor will tend to sweep much of the dcache
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anyway, because the probability history array (typically ushort[7990] or
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ushort[14134]) gets initialized.
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*/
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move t8,v0 # return value from decompression
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lw a0,lxlzma_dst(sp)
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lw a1,lxlzma_dstdone(sp)
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li a2,ICACHE|DCACHE
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li v0,__NR_cacheflush
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syscall
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move v0,t8 # return value from decompression
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lw ra,lxlzma_sv_pc(sp)
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lw tmp,lxlzma_sv_sp(sp)
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jr ra
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subu sp,sp,tmp # un_alloca
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lzma_decode:
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section LZMA_DEC20
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#if 1 /*{*/
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#include "arch/mips/mipsel.r3000/lzma_d.S"
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#else /*}{*/
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#include "arch/mips/mipsel.r3000/jfr-lzma_d.S"
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#endif /*}*/
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section LZMA_DEC30
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break // FIXME
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@ -177,12 +213,6 @@ eof:
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pop t0; sw s0,(t0) // actual length used t0 dst
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pop t0; jr t0; nop
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/* These from /usr/include/asm/unistd.h */
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__NR_Linux = 4000
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__NR_write = 4+ __NR_Linux
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__NR_exit = 1+ __NR_Linux
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__NR_mmap = 90+ __NR_Linux
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msg_SELinux:
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addiu a2,zero,L71 - L70 // length
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bal L72
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