Commit Graph

58 Commits

Author SHA1 Message Date
XMRig
35d9c755e0 Special case for Intel CPUs with 1 MB L2 cache per core. 2019-07-26 16:22:44 +07:00
XMRig
a5e8b31d55 Fixed crash. 2019-07-25 19:27:12 +07:00
XMRig
d4772cbd5d Fixed dataset initialization speed on Linux if thread affinity was used. 2019-07-25 19:11:07 +07:00
XMRig
4a32494060 Added option "init-threads". 2019-07-25 12:20:59 +07:00
XMRig
1d78e7d60d "GET /1/threads" replaced to "GET /2/backends". 2019-07-19 04:22:21 +07:00
XMRig
8ce00adda4 Restored "CPU READY" message. 2019-07-17 14:54:08 +07:00
XMRig
270d3ba6a2 Added class RxVm. 2019-07-10 10:14:33 +07:00
XMRig
f42adafee0 Added classes Rx, RxAlgo, RxCache, RxDataset. 2019-07-10 01:53:05 +07:00